The time sequence of the operation of a 4-bit serial adder is illustrated in Figure 9.33. The sum bit s i, is shifted out to the left-shift register and the carryout bit c i+1 is stored in the state memory of the serial adder for the next two bits. During each clock cycle, two input bits a i and b i are shifted from the two input right-shift registers into the 1-bit full-adder, which adds the two bits and evaluates the sum bit s i and the carryout bit c i+1. A block diagram of a serial adder is shown in Figure 9.32.įigure 9.32 Block Diagram of a Serial Adderįigure 9.33 Time Sequence of the Operation of a 4-bit Serial AdderĪ finite-state machine adder performs the addition operation on the values stored in the input shift registers and stores the sum in a separate shift register during several clockcycles. Two right-shift registers are used to hold the numbers ( A and B) to be added, while one left-shift register is used to hold the sum ( S). In serial adders, pairs of bits are added simultaneously during each clock cycle. A serial adder consists of a 1-bit full-adder and several shift registers. Sequential serial adders are economically efficient and simple to build.
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